The present invention relates to semiconductor power field effect transistors (FETs), and more particularly to structures and methods for forming improved shielded gate FETs.
Shielded gate trench FETs are advantageous over conventional field effect transistor devices in that the shield electrode reduces the gate-drain capacitance (Cgd) and improves the breakdown voltage of the transistor. However, further improvements can be made. There is a need for power FETs with improved performance including lower on-resistance (RDSon), higher blocking voltage, and lower gate charges. Sufficient ruggedness is also important, since the ruggedness defines the safe operating area (SOA) and the unclamped inductive switching (UIS) of the device. Improving these and other characteristics results in very low on-state power losses and switching losses in turn resulting in high power conversion efficiencies in applications such as DC-DC converters.
FIG. 1 is a cross sectional view of a conventional shielded gate trench MOSFET. Trench 110 includes a shield electrode 114 below a gate electrode 118. Shield electrode 114 is insulated from adjacent silicon regions by a shield dielectric 112 which is typically thicker than gate dielectric 120 extending along upper trench sidewalls. The gate and shield electrodes are insulated from one another by a dielectric layer 116 commonly referred to as inter-electrode dielectric or IED.
One problem with the shielded gate trench MOSFET shown in FIG. 1 is that gate electrode 118 typically has sharp bottom corners which with the flat top surface of shield electrode 114 leads to high electric fields in these regions. Additionally, the IED layer must be of sufficient quality and thickness to support the required voltage between the gate electrode and the shield electrode. The IED layer may be formed using various different approaches. The quality, thickness and method used to fabricate the IED dielectric are important as the IED has significant impact on electrical characteristics of the device, such as RDSon, Qgd, and Igss.
Interface trap charges and oxide trap charges in IED layer 116 or at the interface between shield electrode 114 and IED 116 are associated primarily with the method for forming the IED, whether grown or deposited. If the IED dielectric layer is too thin, gate to source shorts may occur. If the dielectric is too thick, it may be difficult to align the diffused body region with the top surface of the IED region to ensure that the gate electrode extends below the bottom surface of the body region. If these two regions are misaligned, then the Qgd will decrease and the RDSon will increase.
Another drawback of conventional power FETs is that the drift region represents up to 40% of the total RDSon, significantly limiting improvements in RDSon. The deeper trenches of shielded gate trench FETs exacerbate this problem by requiring even a thicker drift region. One way to reduce the RDSon is to increase the trench density. This may be achieved by shrinking the cell pitch or the size of devices, to enable more FETs to be formed per square area of silicon. However, reducing the cell pitch is limited by manufacturing and design limitations, such as the minimum critical dimensions of photolithography tools and misalignment tolerances.
Misalignment tolerances may be illustrated using FIG. 1 which shows the p+ heavy body region 106 adjacent to source regions 108. Forming the heavy body and source regions requires their corresponding masks to be aligned to the trench. Misalignment of the masks during source and heavy body formation increases the RDSon of the device. Misalignment also increases the base resistance and the common base current gain of the parasitic BJT, which is formed by source region 108, p-type body region 104 and n-type epitaxial layer 102. A parasitic BJT could be turned on at a very low current, resulting in a poor SOA and lower UIS capability. Accordingly, masking misalignments must be minimized or eliminated in order to reduce the cell pitch and improve the performance characteristics of the power FET.
Thus, there is a need for structures and methods of forming improved shielded gate trench FET structures that eliminate or minimize the above drawbacks associated with known techniques, thus allowing improvements in the performance characteristics of shielded gate power FETs.